Small scale aspects of warm dark matter : power spectra and acoustic oscillations

We provide a semi-analytic study of the small scale aspects of the power spectra of warm dark matter (WDM) candidates that decoupled while relativistic with arbitrary distribution functions. These are characterized by two widely different scales $k_{eq} \sim 0.01\,(\mathrm{Mpc})^{-1}$ and k_{fs}= \sqrt{3}\,k_{eq}/2\,^{1/2} with $^{1/2} \ll 1$ the velocity dispersion at matter radiation equality. Density perturbations evolve through three stages: radiation domination when the particle is relativistic and non-relativistic and matter domination. An early ISW effect during the first stage leads to an enhancement of density perturbations and a plateau in the transfer function for $k \lesssim k_{fs}$. An effective fluid description emerges at small scales which includes the effects of free streaming in initial conditions and inhomogeneities. The transfer function features \emph{WDM-acoustic oscillations} at scales $k \gtrsim 2 \,k_{fs}$. We study the power spectra for two models of sterile neutrinos with $m \sim \,\mathrm{keV}$ produced non-resonantly, at the QCD and EW scales respectively. The latter case yields acoustic oscillations on mass scales $\sim 10^{8}\,M_{\odot}$. Our results reveal a \emph{quasi-degeneracy} between the mass, distribution function and decoupling temperature suggesting caveats on the constraints on the mass of a sterile neutrino from current WDM N-body simulations and Lyman-$\alpha$ forest data. A simple analytic interpolation of the power spectra between large and small scales and its numerical implementation is given.Comment: 47 pages, 17 figures, section with comparison with Boltzmann code

A new partitioning approach for layout synthesis from register-transfer netlists

Most of the IC today are described and documented using heiarchical netlists. In addition to gates, latches, and flip-flops, these netlists include sliceable register-transfer components such as registers, counters, adders, ALUs, shifters, register files, and multiplexers. Usually, these components are decomposed into basic gates, latches, and flip-flops, and are laid out using standard cells. The standard cell architecture requires excessive routing area, and does not exploit the bit-sliced nature of register-transfer components. In this paper, we present a new sliced-layout architecture to alleviate the preceding problems. We also describe partitioning algorithms that are used to generate the floorplan for this layout architecture. The partitioning algorithms not only select the best suited layout style for each component, but also consider critical paths, I/O pin locations, and connections between blocks. This approach improves the overall area utilization and minimizes the total wire length

SLAM : an automated structure to layout synthesis system

SLAM is a structure to layout synthesis system. It incorporates parameterisable bit-sliced and glue-logic generators to produce high density layout. In this paper, we describe a sliced layout architecture and SLAM system. In addition, we present partitioning algorithms for generating the floorplan for such an architecture. The algorithms partition the netlist into component sets best suited for different layout styles such as bit-sliced or strip-oriented logic. Each group is partitioned further into clusters to achieve better area utilization. Several experiments demonstrate that highly dense layouts can be achieved by using these algorithms with the sliced layout architecture

Quantum Computers and Decoherence: Exorcising the Demon from the Machine

Decoherence is the main obstacle to the realization of quantum computers. Until recently it was thought that quantum error correcting codes are the only complete solution to the decoherence problem. Here we present an alternative that is based on a combination of a decoherence-free subspace encoding and the application of strong and fast pulses: ``encoded recoupling and decoupling'' (ERD). This alternative has the advantage of lower encoding overhead (as few as two physical qubits per logical qubit suffice), and direct application to a number of promising proposals for the experimental realization of quantum computers.Comment: 15 pages, no figures. Invited contribution to the proceedings of the SPIE Conference on Fluctuations and Noise. Section 8 contains a new result: how to eliminate off-resonant transitions induced by generic "bang-bang" pulses, by using a special type of "bang-bang" pulse

Layout-driven allocation for high level synthesis

We propose a hypergraph model and a new algorithm for hardware allocation. The use of a hypergraph model facilitates the identification of sharable resources and the calculation of interconnect costs. Using the hyper graph model, the algorithm performs interconnect optimization by taking into account interdependent relationships between three allocation subtasks: register, operation, and interconnect allocations simultaneously. Previous algorithms considered these three tasks serially. Another novel contribution of our algorithm is the exploration of design space by trading off storage units and interconnects. We also demonstrate that traditional cost functions using the number of registers and the number of mux-inputs can not guarantee the minimal area. To rectify the problem, we introduce a new layout area cost function and compare it to the traditional cost functions. Our experiments show that our algorithm is superior to previously published algorithms under traditional cost functions